SR FLIP FLOP

SR Flip-Flop
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A. The SR flip-flop operation is as follows (there is no clock):
1. S=0, R=0 : No Change. Q will not change state (neither will Q')
2. S=0, R=1 : Reset. Q gets reset (goes to 0). Q will be a 1.
3. S=1, R=0 : Set. Q gets set (goes to 1). Q' will be a 0.
4. S=1, R=1 : Not allowed.
B. NOR Implementation
1. Connect the circuit shown in Figure 1. Use DS-1 for S, DS-2 for R, DI-1 for
Q, and DI-2 for Q'.
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S
R
Q'
Q
Figure 1
2. Set S to 0 and R to 1. This resets the flip-flop which means that Q is a 0 and
Q' is a 1. This will always be the case when S=0 and R=1 regardless of the
previous state of Q.
3. Go from S=0 and R=1 to S=0 and R=0. Q stays at 0 because SR=00 is the
no change input combination and the previous state of Q was a 0.
4. Set S to 1 and R to 0. This input combination sets the flip-flop (Q=1, Qi=0)
regardless of the previous state of Q.
5. Go from SR=10 to SR=00. This time Q stays at 1 which confirms that Q
does not change state if S and R are 00.
6. Set S to a 1 and R to a 1. This input combination is disallowed since Q and
Q' are both 0 and are not complements of each other. This input combination
should always be avoided.
7. Do steps 2 through 5 a few more times to get the feel of the operation of the
SR flip-flop. Include changing S and R from 01 to 10 and from 10 to 01.
C. NAND Implementation
1. Connect the circuit shown in Figure 2. Use DS-1 for S, DS-2 for R, and DI-
1 for Q, and DI-2 for Q'. Notice that this implementation is different from
the previous one in that S feeds into the gate whose output is Q and R feeds
into the gate whose output is Q'.
S
R
Q
Q'
Figure 2
2. Repeat steps 2 through 5 of the previous section to verify that this
implementation of the SR flip-flop is equivalent to the NOR
implementation.
3. Set S and R to 11 and notice that Q and Q' are once again not complements
of each other, but this time they are both equal to 1. This is the only
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difference in the two implementations, but causes no problem since SR=11
is a disallowed input combination in both cases.
D. SR Flip-flop with Enable
1. Connect the circuit of Figure 3. Use DS-1 for S, DS-2 for R, DS-3 for
Enable, DI-1 for Q and DI-2 for Q'.
S
R
Enable
Q
Q'
Figure 3
2. Enable=1 enables the S and R inputs. To see what this means, set enable
high and verify that the circuit works exactly like the circuit of Figure 2.
3. Enable=0 disables the inputs. Show this by setting enable low and changing
the S and R inputs. Notice that the outputs will not change regardless of
what changes occur at S and R.
E. SR Flip-flop Truth Table
1. Make out a truth table for the SR flip-flop with the enable. Include columns
for S, R, Enable, Q and Q+.
2. Consult the TTL Date Book for the truth table of 74LS279