Frequency Reuse
The base station antennas are designed to achieve the desired coverage within the particular
cell. By limiting the coverage area to within the boundaries of a cell, the same group of channels
may be used to cover different cells that are separated from one another by distances large
enough to keep interference levels within tolerable limits. The design process of selecting and
allocating channel groups for all the cellular base stations within a system is called frequency
reuse or frequency planning.
In Fig. 1.1 the cells labeled with the same letter use the same group of channels. The frequency
reuse plan is overlaid upon a map to indicate where different frequency channels are used. The
hexagonal cell shape shown is conceptual and is a simplistic model of the coverage for each
base station. The hexagon has been universally adopted since the hexagon permits easy and
manageable analysis of a cellular system. Also considering geometric shapes which cover an
entire region without overlap and with equal area, hexagon has the largest area considering the
distance between the center of a polygon and its farthest perimeter points. The actual footprint
is determined by the contour in which a given transmitter serves the mobiles successfully.
10
Friday, April 8, 2011
The Cellular Concept
The Cellular Concept
The cellular concept[2] was a major breakthrough in solving the problem of spectral congestion
and user capacity. It offered high capacity with a limited spectrum allocation without any major
technological changes. The cellular concept is a system level idea in which a single, high power
transmitter (large cell) is replaced with many low power transmitters (small cells). The area
serviced by a transmitter is called a cell. Each small powered transmitter, also called a base
station provides coverage to only a small portion of the service area. Base stations close to one
another are assigned different groups of channels so that all the available channels are assigned
to a relatively small number of neighboring base stations. Neighboring base stations are
assigned different groups of channels so that the interference between base stations is
minimized. By symmetrically spacing base stations and their channel groups throughout a
service area, the available channels are distributed throughout the geographic region and may be
reused as many times as necessary, so long as the interference between co-channel stations is
kept below acceptable levels.
9
As the demand for service increases, the number of base stations may be increased, thereby
providing additional capacity with no increase in radio spectrum. This fundamental principle is
the foundation for modern mobile communication systems, since it enables a fixed number of
channels to serve an arbitrarily large number of subscribers by reusing the channels throughout
the region. The concepts of frequency reuse, handoff and system capacity are explained in next post
The cellular concept[2] was a major breakthrough in solving the problem of spectral congestion
and user capacity. It offered high capacity with a limited spectrum allocation without any major
technological changes. The cellular concept is a system level idea in which a single, high power
transmitter (large cell) is replaced with many low power transmitters (small cells). The area
serviced by a transmitter is called a cell. Each small powered transmitter, also called a base
station provides coverage to only a small portion of the service area. Base stations close to one
another are assigned different groups of channels so that all the available channels are assigned
to a relatively small number of neighboring base stations. Neighboring base stations are
assigned different groups of channels so that the interference between base stations is
minimized. By symmetrically spacing base stations and their channel groups throughout a
service area, the available channels are distributed throughout the geographic region and may be
reused as many times as necessary, so long as the interference between co-channel stations is
kept below acceptable levels.
9
As the demand for service increases, the number of base stations may be increased, thereby
providing additional capacity with no increase in radio spectrum. This fundamental principle is
the foundation for modern mobile communication systems, since it enables a fixed number of
channels to serve an arbitrarily large number of subscribers by reusing the channels throughout
the region. The concepts of frequency reuse, handoff and system capacity are explained in next post
Thursday, April 7, 2011
SR FLIP FLOP
SR Flip-Flop
………………………………………………………….
A. The SR flip-flop operation is as follows (there is no clock):
1. S=0, R=0 : No Change. Q will not change state (neither will Q')
2. S=0, R=1 : Reset. Q gets reset (goes to 0). Q will be a 1.
3. S=1, R=0 : Set. Q gets set (goes to 1). Q' will be a 0.
4. S=1, R=1 : Not allowed.
B. NOR Implementation
1. Connect the circuit shown in Figure 1. Use DS-1 for S, DS-2 for R, DI-1 for
Q, and DI-2 for Q'.
EE 3714 Flip-Flops
5
S
R
Q'
Q
Figure 1
2. Set S to 0 and R to 1. This resets the flip-flop which means that Q is a 0 and
Q' is a 1. This will always be the case when S=0 and R=1 regardless of the
previous state of Q.
3. Go from S=0 and R=1 to S=0 and R=0. Q stays at 0 because SR=00 is the
no change input combination and the previous state of Q was a 0.
4. Set S to 1 and R to 0. This input combination sets the flip-flop (Q=1, Qi=0)
regardless of the previous state of Q.
5. Go from SR=10 to SR=00. This time Q stays at 1 which confirms that Q
does not change state if S and R are 00.
6. Set S to a 1 and R to a 1. This input combination is disallowed since Q and
Q' are both 0 and are not complements of each other. This input combination
should always be avoided.
7. Do steps 2 through 5 a few more times to get the feel of the operation of the
SR flip-flop. Include changing S and R from 01 to 10 and from 10 to 01.
C. NAND Implementation
1. Connect the circuit shown in Figure 2. Use DS-1 for S, DS-2 for R, and DI-
1 for Q, and DI-2 for Q'. Notice that this implementation is different from
the previous one in that S feeds into the gate whose output is Q and R feeds
into the gate whose output is Q'.
S
R
Q
Q'
Figure 2
2. Repeat steps 2 through 5 of the previous section to verify that this
implementation of the SR flip-flop is equivalent to the NOR
implementation.
3. Set S and R to 11 and notice that Q and Q' are once again not complements
of each other, but this time they are both equal to 1. This is the only
EE 3714 Flip-Flops
6
difference in the two implementations, but causes no problem since SR=11
is a disallowed input combination in both cases.
D. SR Flip-flop with Enable
1. Connect the circuit of Figure 3. Use DS-1 for S, DS-2 for R, DS-3 for
Enable, DI-1 for Q and DI-2 for Q'.
S
R
Enable
Q
Q'
Figure 3
2. Enable=1 enables the S and R inputs. To see what this means, set enable
high and verify that the circuit works exactly like the circuit of Figure 2.
3. Enable=0 disables the inputs. Show this by setting enable low and changing
the S and R inputs. Notice that the outputs will not change regardless of
what changes occur at S and R.
E. SR Flip-flop Truth Table
1. Make out a truth table for the SR flip-flop with the enable. Include columns
for S, R, Enable, Q and Q+.
2. Consult the TTL Date Book for the truth table of 74LS279
JK FLIP FLOPS
JK Flip-Flop
………………………………………………………….
Like the 7474, the 74109 has two flip-flops on the same chip. The difference is that
the 74109 has two JK flip-flops. Use only one of these flip-flops in this part of the
experiment.
A. Asynchronous Preset and Clear
1. Connect power and ground to the 74109. Notice that these connections are
different from other chips. Connect Q and Q' to data indicators. Connect
DS-1 and DS-2 to the preset and clear inputs. Perform the same operations
with the preset and clear inputs of the JK flip-flop as was done with the D
flip- flop.
B. Normal operation using the J, K, and Clock Inputs
1. The JK flip-flop is a positive edge-triggered device which means that the
outputs, Q and Q' will only be affected by the J and K inputs when a low to
high transition is produced at the clock input. Note that for the 74019 the J
input is high true, the K input is low true (note the bar over the K input in
the 74109 data sheet). Use a 7404 inverter to invert the switch input to the
EE 3714 Flip-Flops
4
K input so that both J and K are high true inputs. You may have a 7476 in
your parts kit instead of a 74019 - a 7476 also has two JK flip-flops, but
both J and K are high true inputs so you would not need the inverter with a
7476.
2. The JK flip-flop operation is as follows (assuming that both J,K are high
true - 0 = L, 1 = H):
a. J=0, K=0 : No Change. Q will not change state (neither will Q') when a
negative edge is supplied to the clock.
b. J=0, K=1 : Go to 0. Q will become a 0 (Q' goes to 1) when a negative
edge is supplied to the clock.
c. J=1, K=0 : Go to 1. Q will become a 1 (Q' goes to 0) when a negative
edge is supplied to the clock.
d. J=1, K=1 : Complement. Q gets the complement of its previous state
(as does Q') when a negative edge is supplied to the clock.
C. JK Flip-Flop Truth Table
1. Consult the TTL Data Book for one version of the JK flip-flop truth table.
2. Construct a truth table similar to the one which was made for the D flip-flop
(fill out Table II on lab data sheet). Include columns for J, K, the clock, Q,
preset, clear, and Q+.
………………………………………………………….
Like the 7474, the 74109 has two flip-flops on the same chip. The difference is that
the 74109 has two JK flip-flops. Use only one of these flip-flops in this part of the
experiment.
A. Asynchronous Preset and Clear
1. Connect power and ground to the 74109. Notice that these connections are
different from other chips. Connect Q and Q' to data indicators. Connect
DS-1 and DS-2 to the preset and clear inputs. Perform the same operations
with the preset and clear inputs of the JK flip-flop as was done with the D
flip- flop.
B. Normal operation using the J, K, and Clock Inputs
1. The JK flip-flop is a positive edge-triggered device which means that the
outputs, Q and Q' will only be affected by the J and K inputs when a low to
high transition is produced at the clock input. Note that for the 74019 the J
input is high true, the K input is low true (note the bar over the K input in
the 74109 data sheet). Use a 7404 inverter to invert the switch input to the
EE 3714 Flip-Flops
4
K input so that both J and K are high true inputs. You may have a 7476 in
your parts kit instead of a 74019 - a 7476 also has two JK flip-flops, but
both J and K are high true inputs so you would not need the inverter with a
7476.
2. The JK flip-flop operation is as follows (assuming that both J,K are high
true - 0 = L, 1 = H):
a. J=0, K=0 : No Change. Q will not change state (neither will Q') when a
negative edge is supplied to the clock.
b. J=0, K=1 : Go to 0. Q will become a 0 (Q' goes to 1) when a negative
edge is supplied to the clock.
c. J=1, K=0 : Go to 1. Q will become a 1 (Q' goes to 0) when a negative
edge is supplied to the clock.
d. J=1, K=1 : Complement. Q gets the complement of its previous state
(as does Q') when a negative edge is supplied to the clock.
C. JK Flip-Flop Truth Table
1. Consult the TTL Data Book for one version of the JK flip-flop truth table.
2. Construct a truth table similar to the one which was made for the D flip-flop
(fill out Table II on lab data sheet). Include columns for J, K, the clock, Q,
preset, clear, and Q+.
JK FLIP FLOPS
JK Flip-Flop
………………………………………………………….
Like the 7474, the 74109 has two flip-flops on the same chip. The difference is that
the 74109 has two JK flip-flops. Use only one of these flip-flops in this part of the
experiment.
A. Asynchronous Preset and Clear
1. Connect power and ground to the 74109. Notice that these connections are
different from other chips. Connect Q and Q' to data indicators. Connect
DS-1 and DS-2 to the preset and clear inputs. Perform the same operations
with the preset and clear inputs of the JK flip-flop as was done with the D
flip- flop.
B. Normal operation using the J, K, and Clock Inputs
1. The JK flip-flop is a positive edge-triggered device which means that the
outputs, Q and Q' will only be affected by the J and K inputs when a low to
high transition is produced at the clock input. Note that for the 74019 the J
input is high true, the K input is low true (note the bar over the K input in
the 74109 data sheet). Use a 7404 inverter to invert the switch input to the
EE 3714 Flip-Flops
4
K input so that both J and K are high true inputs. You may have a 7476 in
your parts kit instead of a 74019 - a 7476 also has two JK flip-flops, but
both J and K are high true inputs so you would not need the inverter with a
7476.
2. The JK flip-flop operation is as follows (assuming that both J,K are high
true - 0 = L, 1 = H):
a. J=0, K=0 : No Change. Q will not change state (neither will Q') when a
negative edge is supplied to the clock.
b. J=0, K=1 : Go to 0. Q will become a 0 (Q' goes to 1) when a negative
edge is supplied to the clock.
c. J=1, K=0 : Go to 1. Q will become a 1 (Q' goes to 0) when a negative
edge is supplied to the clock.
d. J=1, K=1 : Complement. Q gets the complement of its previous state
(as does Q') when a negative edge is supplied to the clock.
C. JK Flip-Flop Truth Table
1. Consult the TTL Data Book for one version of the JK flip-flop truth table.
2. Construct a truth table similar to the one which was made for the D flip-flop
(fill out Table II on lab data sheet). Include columns for J, K, the clock, Q,
preset, clear, and Q+.
………………………………………………………….
Like the 7474, the 74109 has two flip-flops on the same chip. The difference is that
the 74109 has two JK flip-flops. Use only one of these flip-flops in this part of the
experiment.
A. Asynchronous Preset and Clear
1. Connect power and ground to the 74109. Notice that these connections are
different from other chips. Connect Q and Q' to data indicators. Connect
DS-1 and DS-2 to the preset and clear inputs. Perform the same operations
with the preset and clear inputs of the JK flip-flop as was done with the D
flip- flop.
B. Normal operation using the J, K, and Clock Inputs
1. The JK flip-flop is a positive edge-triggered device which means that the
outputs, Q and Q' will only be affected by the J and K inputs when a low to
high transition is produced at the clock input. Note that for the 74019 the J
input is high true, the K input is low true (note the bar over the K input in
the 74109 data sheet). Use a 7404 inverter to invert the switch input to the
EE 3714 Flip-Flops
4
K input so that both J and K are high true inputs. You may have a 7476 in
your parts kit instead of a 74019 - a 7476 also has two JK flip-flops, but
both J and K are high true inputs so you would not need the inverter with a
7476.
2. The JK flip-flop operation is as follows (assuming that both J,K are high
true - 0 = L, 1 = H):
a. J=0, K=0 : No Change. Q will not change state (neither will Q') when a
negative edge is supplied to the clock.
b. J=0, K=1 : Go to 0. Q will become a 0 (Q' goes to 1) when a negative
edge is supplied to the clock.
c. J=1, K=0 : Go to 1. Q will become a 1 (Q' goes to 0) when a negative
edge is supplied to the clock.
d. J=1, K=1 : Complement. Q gets the complement of its previous state
(as does Q') when a negative edge is supplied to the clock.
C. JK Flip-Flop Truth Table
1. Consult the TTL Data Book for one version of the JK flip-flop truth table.
2. Construct a truth table similar to the one which was made for the D flip-flop
(fill out Table II on lab data sheet). Include columns for J, K, the clock, Q,
preset, clear, and Q+.
Thursday, March 31, 2011
signals processing in biometrics
Digital Signal Processing In Biometrics
Biometrics is the technology used to analyze biological data. Its most recent application is in the area of security where the biological data of a person is used for personal identification and authentication before the person is allowed to proceed to enter a building or do any business transactions. Fingerprint, iris scan and facial features are among some of the human biometrics used.
The development of single chip DSP microcontroller that processes the electrical signals generated by the transducers such as digital camera CCD devices and fingerprint sensors have helped to speed up the processing power and hence make authentication easy and efficient.
One of the industry leader in DSP technology is Texas Instruments which have developed dedicated microcontroller for DSP application. The technology that have been developed in Biometrics are discussed in great details and is a great source of design references for students or even electronics designers who are keen to develop a biometrics based DSP system.
Biometrics is the technology used to analyze biological data. Its most recent application is in the area of security where the biological data of a person is used for personal identification and authentication before the person is allowed to proceed to enter a building or do any business transactions. Fingerprint, iris scan and facial features are among some of the human biometrics used.
The development of single chip DSP microcontroller that processes the electrical signals generated by the transducers such as digital camera CCD devices and fingerprint sensors have helped to speed up the processing power and hence make authentication easy and efficient.
One of the industry leader in DSP technology is Texas Instruments which have developed dedicated microcontroller for DSP application. The technology that have been developed in Biometrics are discussed in great details and is a great source of design references for students or even electronics designers who are keen to develop a biometrics based DSP system.
Tuesday, December 14, 2010
Fault in new cartesian sign conventions
If we analye, while proving mirror,lens or lens makers formula we make use of sign coventions but when we solve numericals we again make use of sign conventions why? This creates problem for new cartesians sign conventions
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